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Editorial

Peggy Aycinena
EDA Weekly
The Best of Times, The Worst of Time: Part 2 Since Part 1 of this article was published on October 13th, events have begun to overwhelm. The dramatic speed with which the …

Mark Gilbert
Careers Corner
Remember that kids' nursery rhyme LAYOFFS, FREEZES, GENERAL DOWNTURN… O MY?

Dr. Russ Henke & Dr. Jack Horgan
EDA & IP Commentary
Commentary: Electronics IP Industry - A November 2008 Update

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Jobs

Circuit Design Engineer for Sun Microsystems at Santa Clara, CA

Verification Engineer - Microprocessors for Sun Microsystems at Santa Clara, CA

Technical Collateral Specialist for Springsoft, Inc at San Jose, CA

Chip Integration Lead for Sun Microsystems at Santa Clara, CA

Senior Design Automation Engineer / Project Lead for Sun Microsystems at Santa Clara, CA

Chief Architect for Sun Microsystems at Santa Clara, CA

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Books For Sale

Digital Logic and Microprocessor Design with VHDL, by Enoch O. Hwang.

Digital Electronics Laboratory Experiments Using the Xilinx XC95108 CPLD with Xilinx Foundation: Design and Simulation Software (2nd Edition), by James Stewart, Chao-Ying Wang.

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Upcoming Events

DASIP 2008 at Université Libre de Bruxelles Belgium - Nov 24 - 26, 2008

SPS/IPC/DRIVES 2008 at Karl-Schönleben-Strasse Nuremberg Germany - Nov 25 - 27, 2008

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Tutorials

The Role of B2 Spice A/D v4

MT-005: Noise Power Ratio (NPR) – A 65-Year Old Telephone System Specification Finds New Life in Modern Wireless Applications

ADC Architectures III: Sigma-Delta ADC Basics

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